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Switch mode regulators; l0 W* }0 n3 I1 `4 ?( m. }
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators7 x, k# A$ K! t8 O0 }! \
receive power from VBAT or VCHG under application software control.
0 a2 n3 \% h7 O, KThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC30401 z- i! F& G$ i! r' r* v+ J
VFBGA and the flash memory. The System SMPS can supply power to external components.4 b& b, l& C, z% |1 M
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches- s- O4 k3 `8 s# c
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.. Z0 R# k) `; r5 w
The SMPS both have three operating modes:2 k( n8 ], H" Q, P5 I
■ Normal (PWM)6 c- Y5 m2 K- w% {/ `
■ Two low-power modes with reduced current capability:& r d: ?& h4 X! E8 n% V6 E6 z
□ PFM/ e7 |- Z) x* D( A, v
□ ULP
2 L% e6 I& Q8 `0 P! g ]Normally the system auto switches, but this is optionally disabled.
* r4 p( V) P6 p1 r' _The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
: r) F1 [. y# ZFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
# h: ^7 }" M) R' A+ l" K$ LCH285-1).% E$ i: Q, ^4 Y% c. J+ P3 N) v
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have6 P1 h$ Y3 C. n* I5 v5 h I9 F4 |, D
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.3 K! Y% _+ {' A0 `- w* y2 n
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.5 r' D1 ]: |% `: I6 B
3 e& m8 u- F0 A/ c. `
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